EDN

Static verification needs a parallel approach

Next generation communications and consumer electronics products, especiallythose based on 90-nanometer technology and below, will include chips thatexceed 70 million gates. We providers of EDA tools ...
Business Wire

Aldec Provides Static Verification for RISC-V Designs with the Latest Release of ALINT-PRO

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added a RISC-V focused static verification ...
Semiconductor Engineering

Power-Aware Intent And Structural Verification Of Low-Power Designs

Cell-level and pin-level attributes from Liberty are mandatorily required for accurate PA-Static verification at the GL-netlist (post-synthesis) and PG-netlist (post P&R) levels of the design.
Semiconductor Engineering

Shift Left Power-Aware Static Verification

Next-generation SoCs with advanced graphics, computing, machine learning (ML) and artificial intelligence (AI) capabilities are posing new unseen challenges in Low Power Verification. These techniques ...
EDN

Synopsys Bridges Design and Verification with Next-Generation Static and Formal Technology for Verification Compiler

Next-generation static and formal verification technology now available as part of the Verification Compiler™ product and as standalone solutions Solutions provide 3X to 5X better performance and ...
Embedded

Next-generation of SPARK static verification toolset released

Altran and AdaCore have released an enhanced upgrade to their integrated development and verification environment for the ADA-based SPARK language, Version 14.0. According to Keith Williams, Group ...