EDN

FPGA-Based FIR Filters using Distributed Arithmetic

M. Martinez-Peir, R. Colom, F. Ballester, and R. Gadea are teachers with a focus on digital applications at the Technical University of Valencia, Spain. They are currently working on video compression ...
Design-Reuse

Systolic FIR Filter Based FPGA

In this paper, we first review in detail the basic building blocks of reconfigurable devices, essentially, the field-programmable gate arrays, then we describes a high-speed, reconfigurable Systolic ...
TechRepublic

Design and Implementation of DA-Based Reconfigurable FIR Digital Filter Using FPGA Technology for Wireless Sensor Network

In this paper, the authors present the design optimization of one- and two-dimensional fully pipelined computing structures for area-delay power-efficient implementation of Finite Impulse Response ...
Electronics Weekly

DSP versus FPGA

In considering the design option for DSP vs. FPGA it is helpful to compare both architectures in a FIR filter application, writes Reg Zatrepalek One of the most widely used digital signal-processing ...
EDN

IP suites target LatticeECP3 FPGAs

Five IP suites are available to accelerate the design of systems using the LatticeECP3 FPGA family. The five suites are PCI Express, Ethernet Networking, DSP, Video & Display, and Value. The Value ...
Design-Reuse

Optimizing Up/Down Conversion with FPGA Techniques

Digital upconverters (DUCs) and digital downconverters (DDCs) are important components of every modern wireless base station design. While many DUC and DDC designs are available, there is a clear call ...